In this case the routing segment routing_segment_lut_n616_output_0_0_to_lut_n497_input_0_4 has a delay of 312.648 ps, while the LUT lut_n452 has a delay of 261 ps from each input to the output. Here we see the timing description of the cells in Listing 19.
The SDF defines all the delays in the circuit using the delays calculated by VPR’s STA engine from the architecture file we provided.
0 kommentar(er)
